EHA Soft Solutions (EHA), has been selected by Quality Employment Credentialing (QEC) to provide the organization with customized automated risk management and mitigation software. EHA will first implement the software at QEC test sites in Pennsylvania, New York and Texas before deploying the solution nationwide.
The news coincides with a business reception today in Washington, DC hosted by Enterprise Ireland, the Government Agency responsible for driving leadership and growth for innovative Irish companies in international markets. The event was one of several associated with a trade mission to the U.S. led by Ireland's Prime Minister, Brian Cowen.
QEC was formed because increasing risk and liability, identity theft, and the high costs to hire healthcare providers have become a growing problem for hospitals, nursing homes, staffing agencies and other employers of the healthcare workforce. QEC intends to cut costs and reduce risk to the industry and consumers by introducing a new standard of hiring best-practices. The company's approach replaces the inefficient protocols of piecing together hiring elements such as background checks, drug screening and competency testing, with a new streamlined model that compiles the information in a highly secure and independent global clearing house. The result is a new approach that substantially reduces the risk and exposure to liability of a hiring mistake.
Said, QEC chairperson, Colleen Mills, "With EHA, we have found a partner with superior software solutions that can support our goal to transform healthcare hiring practices and reduce the threat and liability associated with hiring mistakes. We're very pleased to be working with EHA."
For more than a decade, EHA has provided advanced integrated risk management systems that support regulatory guidelines, including occupational health and safety, food safety, quality and the environment. The company's software solutions are an ideal fit to support QEC's ambitious mission, according to Mike Shackleford, vice president of operations at EHA. "By significantly reducing risk and exposure to liability, the QEC system will improve overall quality of care and reduce staff turnover, meaning substantial savings for healthcare providers that are struggling with escalating costs in today's env
Tuesday, 17 March 2009
Thermal Engineering Associates, Inc. (TEA) announces the immediate availability of a new thermal test chip, TTC-1002, that complies with standard EIA/JESD51-4 and is flexible enough to meet virtually all of the requirements for general purpose semiconductor thermal testing applications. Wafers and cell arrays may be ordered for wire bond or bump connection applications. Thermal test chips are widely used to eliminate electronics heat dissipation problems through package/system level thermal characterization, package assembly process optimization, and heat sink thermal solution evaluation.
Thermal test chips are semiconductor devices that can deliver precise thermal loads to specific geographic areas of a semiconductor package or printed circuit board (PCB) in order to simulate the thermal performance characteristics of the subsystem. Applications for thermal test chips include:
-- Package thermal requirements testing
-- Package thermal simulation and verification
-- Package mechanical stress testing
-- Power mapping of thermal effects
-- PCB level thermal simulation
-- System level thermal simulation
TEA founder and President, Bernie Siegal, has been supplying thermal test and measurement products and services for over 40 years. "Our new thermal test chip finally meets all JEDEC and general user requirements," said Siegal, "I have worked very hard over the last 10 years to come up with a thermal test chip that is nearly perfect with regard to maximizing the heated area in each cell, uniformity of cell heating, easy access to strategically placed measurement diodes, accurate measurements, and flexibility in simulating the widest range of application specific semiconductors."
The TTC-1002 is based upon a unit cell design in which a cell may be used individually or combined in a matrix of up to 40 x 40. Each cell is 2.5mm on a side and regardless of the size of the cell matrix, there is periphery access for all heating and Kelvin enabled measurement connections. Strategically placed diode sensors enable thermal measurements in the center, center periphery and all diagonals, regardless of the size or configuration of the cell array. Two individual metal film heating elements cover 87% of the die surface for uniform heating of each half of the cell, as needed. The two heating elements may be connected in series or in parallel.
Thermal test chips are semiconductor devices that can deliver precise thermal loads to specific geographic areas of a semiconductor package or printed circuit board (PCB) in order to simulate the thermal performance characteristics of the subsystem. Applications for thermal test chips include:
-- Package thermal requirements testing
-- Package thermal simulation and verification
-- Package mechanical stress testing
-- Power mapping of thermal effects
-- PCB level thermal simulation
-- System level thermal simulation
TEA founder and President, Bernie Siegal, has been supplying thermal test and measurement products and services for over 40 years. "Our new thermal test chip finally meets all JEDEC and general user requirements," said Siegal, "I have worked very hard over the last 10 years to come up with a thermal test chip that is nearly perfect with regard to maximizing the heated area in each cell, uniformity of cell heating, easy access to strategically placed measurement diodes, accurate measurements, and flexibility in simulating the widest range of application specific semiconductors."
The TTC-1002 is based upon a unit cell design in which a cell may be used individually or combined in a matrix of up to 40 x 40. Each cell is 2.5mm on a side and regardless of the size of the cell matrix, there is periphery access for all heating and Kelvin enabled measurement connections. Strategically placed diode sensors enable thermal measurements in the center, center periphery and all diagonals, regardless of the size or configuration of the cell array. Two individual metal film heating elements cover 87% of the die surface for uniform heating of each half of the cell, as needed. The two heating elements may be connected in series or in parallel.
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